[1] Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, and Yunheung Paek. "Preprocessing Strategy for Effective Modulo Scheduling on Multi-Issue Digital Signal Processors," In the Proceedings of the 16th International Conference on Compiler Construction, March, 2007, Braga, Portugal.

[2] Gang-Ryung Uh, Robert Cohn, Bharadwaj Yadavalli, Ramesh Peri, and Ravi Ayyagari. "Analyzing Dynamic Binary Instrumentation Overhead." In the Proceedings of the Workshop on Binary Instrumentation and Applications, October, 2006, San Jose, USA.

[3] Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, and Yunheung Paek. "Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs." In the Proceeding of the 1^st International Workshop on Embedded Software Optimization, August, 2006.

[4] Gang-Ryung Uh, Yuhong Wang, David Whalley, and et al. "Compiler Transformations for Effectively Exploiting a Zero Overhead Loop Buffer," In Software Practice & Experience, Volume 35, pages 393-412, 2005.

[5] W. Kreahling, D. Whalley, M. Bailey, X. Yuan, Gang-Ryung Uh, R. Van. "Branch Elimination via Multi-Variable Condition Merging," Software Practice & Experience, Volume 35, pages 51-74, 2005.

[6] Wankang Zhao, Prasad Kullkarni, David Whalley, Christopher Healy, Frank Mueller, Gang-Ryung Uh. "Tuning WCET of Embedded System," In the Proceedings of IEEE 10^th Real-Time and Embedded Technology and Applications Symposium, May 2004, Toronto, Canada.

[7] Jinhwan Kim, Yunheung Paek, Gang-Ryung Uh. Uh: "Code Optimization for a VLIW-style network processing unit," In Software Practice & Experience, Volume 34, pages 847-874, 2004 (ISSN Number: 0038-0644).

[8] Gang-Ryung Uh. "Tailoring Software Pipelining for Effective Exploitation of Zero Overhead loop buffer," In the Proceedings of the 7^th International Workshop on Software and Compilers for Embedded Systems (SCOPES 2003), September 24-26, 2003, Vienna, Austria.

[9] W. Kreahling, D. Whalley, M. Bailey, X. Yuan, Gang-Ryung Uh, R. Van. "Branch Elimination via Multi-Variable Condition Merging," In the Proceedings of European Conference on Parallel and Distributed Computing (EuroPar03), August 26-29, 2003, Klagenfurt, Austria.

[10] Minghui Yang, Gang-Ryung Uh, David Whalley. "Efficient and Effective Branch Reordering Using Profile Data," In ACM Transactions on Programming Languages and Systems (TOPLAS),Volume 26, Number 6, pages 667-697, 2002.

[11] J. Kim, S. Jung, Y. Paek, and Gang-Ryung Uh. "Experience with a Regargetable Compiler for a Commercial Network Processor," In the Proceedings of the 2002 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, 2002, Grenoble, France.

[12] Gang-Ryung Uh, Yuhong Wang, David Whalley, and et al. "Techniques for Effectively Exploiting a Zero Overhead Loop Buffer," In the Proceedings of the 9th International Conference on Compiler Construction (CC'2000), pages 157-172, March 2000, Berlin, Germany.

[13] Gang-Ryung Uh, Yuhong Wang, David Whalley, and et al. "Effective Exploitation of a Zero Overhead Loop Buffer," In the Proceedings of ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, pages 10-19, May 1999, Atlanta, USA.

[14] Gang-Ryung Uh and David Whalley. "Effectively Exploiting Indirect Jumps," In Software Practice & Experience, December 1999, pages 1061-1101.

[15] Minghui Yang, Gang-Ryung Uh, David Whalley. "Improving Performance by Branch Reordering," In the Proceedings of ACM SIGPLAN Conference on Programming Language Design and Implementation, pages 130-141, June 1998, Montreal, Canada.

[16] Gang-Ryung Uh, David Whalley. "Coalescing Conditional Branches into Efficient Indirect Jumps," In the proceedings of International Static Analysis Symposium, pages 315-329, September 1997, Paris, France.